1. Field of the Invention
This invention relates generally to semiconductor devices, and more specifically, to an improved 4T static RAM cell for low power CMOS applications.
2. Discussion of the Prior Art
FIG. 1(a) illustrates a schematic of a 4T SRAM cell 10 according to the prior art. In the prior art SRAM cell 10, a PFET transistor 15 operating under control of the wordline (W/L) conducts the bitline voltage to the internal node 18 of the cell comprising NFET transistor 20a, 20b in a cross-coupled latch configuration. That is, when the W/L gate goes low for read applications, the low internal node within the cell pulls one of the two bitlines low through the W/L device and pull-down transistors, e.g., 15 and 20a. When writing data, the bitline (B/L) voltage is conducted to the internal nodes 18, 19. Operations regarding writing and reading of data are well known to skilled artisans. It is the case that, in the prior art 4T SRAM cell 10, the bit lines additionally function to remain high (except in write or read applications) to allow each PFETs to act as a resistor by virtue of the leakage current (Ioff leakage) provided by the PFET 15 when turned off (wordline is high). That is, the voltage at the internal node 18 is maintained by the high B/L when PFET 15 is turned off. In view of FIG. 1(a), it is understood that one of the internal nodes is going to be high 18, the other internal node will be low 19 and that constitutes either a logic one (1) or zero (0) depending on the predetermined design convention. The device of FIG. 1(a) is described in greater detail in a reference entitled xe2x80x9cA 1.9 xcexcm2 Loadless CMOS Four-Transistor SRAM Cell in a 0.18-xcexcm Logic Technologyxe2x80x9d to K. Noda, K. Matsui, et al. I.E.D.M. 1998, pp. 643-646 which illustrates how the 4T cell may be designed where the internal node can be pulled up by the off current leakage of the wordline PFET only when the bit lines B/L are kept precharged high. The requirement that all the array B/Ls remain high for maintaining the state of the 4T SRAM cell is undesirable for low power CMOS applications. FIG. 5(a) is a further schematic depiction of the prior art 4T SRAM cell of FIG. 1(a) which illustrates the reliance on PFET Ioff resistances R1 and R2 from the B/L""s precharged to a high voltage to the internal nodes 18 and 19.
It would thus be highly desirable to provide a 4T SRAM cell that does not require the bitline to remain at a high level, thus enabling reduction of power consumption requirements for the SRAM cell.
It would further be highly desirable to provide a 4T SRAM cell having a PFET gate oxide layer connecting the wordline that exhibits a resistance property when a wordline (W/L) voltage is applied, the gate oxide layer conducting leakage current for biasing an internal node of the SRAM cell in order to maintain the static cell contents.
Furthermore, it would be highly desirable to implement in a CMOS circuit generally, a gate oxide layer that exhibits a temperature independent resistance property for use in circuit applications.
It is an object of the present invention to provide in CMOS circuits generally a gate oxide layer that exhibits a nearly temperature independent resistance property. Specifically, the gate oxide layer is biased to provide a quantum tunneling leakage current that is proportional to the bias voltage applied and the thickness of the oxide layer. The amount of leakage, e.g., in picoamperes/per unit area is the measure of resistance and is proportional to the gate oxide layer thickness.
Advantageously, utilizing such a gate leakage current property, the voltage of the internal node of the 4T SRAM cell of FIG. 1 may be derived from the wordline which, for the majority of time, is always held high. Consequently, the bitline voltages may be kept low or at Vdd/2, which significantly reduces power consumption of the SRAM array in operation. Additionally, there will be a reduced chance of read disturbance associated with fluctuations in the B/L voltages.
It is contemplated that other CMOS devices may exploit the resistive property provided by such gate oxide layers.